1. Field of the Invention
The present invention relates to a programmable semiconductor device.
2. Description of the Related Art
In semiconductor integrated circuits such as a normal central processing unit (CPU), circuit design is fixed and cannot be changed after manufacturing. In contrast, in semiconductor integrated circuits called programmable logic devices (PLDs), since a logic circuit is composed of an adequate number of logic cells and the logic cells can be interconnected by an electric switch (a programming unit or a switch), interconnections between the logic cells can be changed as needed after manufacturing (see Patent Documents 1 and 2).
Thus, since circuit configurations can be changed by users, PLDs have high versatility and allow great reductions in time and cost spent on circuit design and development.
One of techniques competing with a PLD technique is a gate array. This is an approach by which, over a wafer, components examples of which are standard logic elements such as NAND gates and NOR gates, transistors, and passive elements such as resistors are placed at predefined positions and a metal wiring layer is formed thereover to connect the components to each other, thereby completing a semiconductor circuit. This approach differs from a PLD technique in that connections between components are formed by a metal wiring.
Thus, to complete a semiconductor device by a gate array, only a mask for a metal wiring is ordered and a metal wiring layer is formed using this mask. Although circuit configurations cannot be changed after a semiconductor device is completed, a gate array has been more widely used than a PLD technique because a gate array requires a comparatively smaller amount of investment in small-quantity production and the like.
In recent years, however, as circuit line width is decreased, a gate array has not paid unless considerable quantity of production can be expected, because masks for metal wirings become much more expensive. Therefore, in a gate array, circuit line width has not fallen below 130 nm for the last few years.
In contrast, in PLDs, in which circuits are composed of electric programming units, circuit line width has been 40 nm or less because masks are not required. Further, a PLD technique needs a smaller amount of investment than a gate array. Accordingly, even semiconductor devices that would have been manufactured by a gate array in conventional cases began to be manufactured by a PLD technique.